1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of testing thereof. In particular, the present invention relates to a nonvolatile semiconductor memory device having a memory cell of a field effect transistor type, and a method of testing thereof.
2. Description of Related Art
A CHE (Channel Hot Electron) method is known as a programming method for an NOR type flash memory. According to the CHE method, programming is performed by injecting hot electrons generated in the vicinity of a drain of a memory cell into a floating gate. Also, an FN (Fowler-Nordheim) method is known as a programming/erasing method for a flash memory. According to the FN method, a high voltage is applied between a well or source and a control gate, and thereby an FN current flows between the well or source and the control gate. Due to the FN current, electrons are injected into the floating gate or electrons are extracted from the floating gate.
In the flash memory, erasing is performed collectively with respect to a group of memory cells included in one block. When the erasing is performed, electrons are extracted from the floating gate and thus a threshold voltage of the memory cell is decreased. One of issues relating to the erasing is “over-erasing”. The over-erasing is a phenomenon that the threshold voltage of the memory cell becomes 0 V or less (depression level) as a result of the erasing operation. Since an off-leakage current flows from the memory cell in the depression state, the over-erased state needs to be resolved. Therefore, “programming back” is performed with respect to the over-erased memory cell.
A technique related to the programming back is described in Japanese Laid-Open Patent Application JP-2002-25279A. According to an erasing method described in the patent document, the erasing is performed in units of block on the basis of the FN method. More specifically, the erasing method includes the following three stages. The first stage: a first erase pulse is applied, and the threshold voltage of every memory cells in a block is set to be a voltage that is higher than 0 and equal to or lower than a first predetermined voltage corresponding to an erase state. The second stage: a second erase pulse is applied, and the above-mentioned threshold voltage is further decreased to a voltage equal to or lower than a second predetermined voltage that is lower than the first predetermined voltage. The third stage: a programming back pulse is applied, and the above-mentioned threshold voltage is increased to a voltage that is higher than 0.
The inventor of the present application has recognized the following points. In general, a group of memory cells included in a block of a flash memory has variation in erase characteristics. Among them there are a memory cell which is hardly over-erased and a memory cell which tends to be over-erased. Also, a defective memory cell in which a desired structure is not appropriately formed can be generated in a manufacturing process. It is desirable that the memory cell that tends to be over-erased and the defective memory cell as mentioned above are detected accurately in a test stage. If only such the memory cell having a defect is detected, a block including the detected memory cell can be replaced with a redundancy block. In that case, it is not necessary to eliminate a manufactured memory chip, which improves yield.
Meanwhile, if the memory cell having a defect is not detected accurately in the test stage, the memory chip is eventually eliminated as an operation defective product. This causes reduction of the yield. Alternatively, if the memory chip is not eliminated as an operation defective product, the memory chip may fail during actual use. This causes deterioration of reliability of the memory chip. In either case, it is important to accurately detect the memory cell having a defect in the test stage. That is to say, a technique that improves screening accuracy is desired.